Analysis of an AC-DC Valley-fill Power Factor Corrector (VFPFC) Dylan Dah-Chuan Lu
Analysis of an AC-DC Valley-fill Power Factor Corrector (VFPFC) 23 Analysis of an AC-DC Valley-fill Power Factor Corrector (VFPFC) Dylan Dah-Chuan Lu1 , Non-member ABSTRACT The passive power factor correction approach is attractive for low power applications due to low cost, high efficiency, excellent reliability, simple circuit design and no EMI generated. This paper presents a novel passive inductorless power factor corrector by using valley-fill circuit. Conditions of the proposed Valley-Fill Power-Factor-Corrector (VFPFC) to reach maximum power factor are discussed. Effectiveness of power factor correction by the proposed VFPFC is shown by simulation and is experimentally verified by a 50W prototype (with 93% efficiency and 0.95 power factor). Design guidelines for the VFPFC are also given. Keywords: Power Factor, Total Harmonic Distortion, Voltage-Doubler 1. INTRODUCTION Owing to the growing concern of harmonic input currents drawn from AC mains by the conventional single-phase diode rectifier (i.e. a bridge-diode rectifier with a large bulk capacitor connects to its output) in a power supply, many active and passive approaches in obtaining power factor correction have been proposed and analyzed in existing literature. Although the active power factor correction approach generally has higher power factor (¿0.99), lower total harmonic distortion (¡ 5%) and smaller in size over the passive power factor correction approach, the drawbacks are higher cost, more complicated circuit design, lower efficiency, and many EMI problems. In general, the passive power factor correction approach eliminates the drawbacks of active power factor correction approach stated above. It is more suitable for low-power (≤ 300W) applications  because the choke and storage capacitor used can keep to reasonable sizes and cost while fulfilling hold-up time requirement and line-harmonic standards. Large LC filters are used to achieve high power factor in , these make the power supply bulky and heavy. Capacitor-diode block rectifiers in - can improve power factor with reduction in volume. This rectifier is made up of one stage to n stages voltage-doublers. Manuscript received on March 30, 2007 ; revised on July 23, 2007. 1 The author is with the School of Electrical and Information Engineering, The University of Sydney, NSW 2006, Australia., Email: [email protected] The fewer the stages of voltage-doublers it has, the higher the power factor it can obtain as the input current duration is extended. However, there is an increase in the output voltage ripple. Therefore a compromise must be made between output ripple voltage and power factor. The reasonable stages of voltagedoubler is found to be two when considering components count, power factor and output ripple voltage. Moreover, according to , inserting small capacitors between the bridge-diode-rectifier and input ends also help reduce total harmonic distortion (THD) and improves power factor (PF). In this paper, a novel valley-fill power-factor- corrector (VFPFC) is presented and analyzed. The objectives of this paper are to study the proposed VFPFC for input current shaping (in Section 2 and 3) and to advance a design tool (in Section 4) so as to select the best combinations of capacitances and resistances under desired output power and power factor. Simulation and experimental results (in Section 4) are provided as well. 2. OPERATION PRINCIPLE The proposed VFPFC circuit, as shown in Fig.1, is inserted between the bridge-diode rectifier and the load. The operation principle can be explained with the aid of the waveforms given in Fig. 2 and is depicted as follows. At time t1-t2: The line voltage is slightly higher than the valley-fill voltage (i.e. VC1 + VC2 , VC3 + VC4 or VC1 + VC4 ) and the bridge diodes conduct. Input current flows to the output load directly. (Note: Vcx means voltage across capacitor CX, for X equals 1, 2, 3 or 4.) At time t2-t3: The line voltage continues to rise and go slightly above the voltage sum, VC1 + VC3 + VC4 or VC1 + VC2 + VC4 , the capacitor pair with lower voltage, or smaller capacitance, will be charged up first. If C2 > C3, charging current will flows through C1-D14-R3C3-C4 until C3 voltage is equal to C2 voltage. Then C2 and C3 are charged in parallel. If C2 < C3, C2 will charge up first, and if C2 = C3, they will start charging up at the same time. The input current charges the capacitors as well as flows to the load. At time t3-t4: The input current flows to the load only since all capacitors are fully charged. Unlike the conventional large bulk capacitor for which once it has been fully charged it will stay at the peak input 24 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 3. CIRCUIT ANALYSIS OF THE VFPFC 3. 1 Total harmonic distortion (THD) and power factor (PF) Fig.1: circuit Proposed valley-fill power factor corrector voltage and the input current ceases flowing as the input voltage is decaying, the input current can still flow to the load in this circuit because the valleyfill voltage stays around two-third of the peak input voltage, assuming the capacitance are large enough to hold the output voltage. Thus the conduction time for bridge diodes are lengthened compared to the conventional rectifier. At time t4-t5: When the input voltage decreases and falls below two-third of the input peak voltage or the voltage that VFPFC stays, the input current stops flowing because the bridge diodes are reversed biased. Instead, the capacitors pairs discharge in series to provide the output current. Again, depending on the capacitance of the capacitors pair, the one with smaller capacitance will discharge first. At time t5-t6: Line voltage changes direction but is lower than the valley-fill voltage. However, input current still flows through the path R1-CIN2-D2. The charging/discharging cycle repeats at the next half line cycle when the input voltage is higher than the voltage sum of VC1 +VC2 , VC3 +VC4 or VC1 +VC4 . Fig.2: Important waveforms of the VFPFC by simulation (Assuming C2=C3=C/2 & C1=C4=C). Upper: Input voltage, Vin and current, Iin and output voltage, Vo ; Lower: VFPFC diodes current, ID11−D15 To show the significant improvement in THD and PF of the VFPFC, a VFPFC with 200W output power and a conventional rectifier with the same output power are put into simulation. The output capacitance of the conventional rectifier and the VFPFC are chosen according to the 10% voltage drop during discharge period. The input voltage is 156 V(rms). The capacitances of them are summarized as follows: PFC Circuit Conventional VFPFC Value Output capacitance = 54µF C1/C4 = 232µF; C2/C3 = 116µF Fast Fourier Transform of the input currents of both circuits has been done and shown in Fig. 3. From Fig. 3, it is shown that the third harmonic component of the conventional rectifier contributes most to the input harmonic currents and hence the main cause to low power factor and high THD. However, when using the proposed VFPFC, not only the third harmonic component is reduced by 79% but the rest of the harmonic components are suppressed as well. Also, the THD is reduced from 92% to 34% and power factor is raised from 0.62 to 0.88. The reasons for THD reduction and power factor improvement are explained as follows. Firstly, according to the nonlinear property of the VFPFC, the effective capacitance is changing throughout the line input period. The effective capacitance of the VFPFC is the smallest when charging up, giving smaller peak capacitor current and thus smaller RMS value of the input current. For example, assuming that all capacitor values are C, during charge up the effective capacitance is C1//(C2+C3)//C4 which is equal to 2C/5. On the other hand, the effective capacitance is the largest during discharge. The effective capacitance is C and this prevents the output voltage from dropping quickly. Moreover, since the VFPFC holds at around two-third of the peak input voltage, the bridge-diode conduction time is made longer compared with the conventional rectifier. Secondly, as discussed in , the small capacitor CIN0 compensates the fundamental reactive power (Qf) and absorbs the harmonic distortion power (D) to yield higher power factor (PF) and lower THD. Actually, these can be shown according to the following equations respectively: Pavg PF = q Pavg 2 + Qf 2 + D2 (1) pP ∞ T HD = 2 n=2 In,harmonics(rms) I1,f undamental(rms) (2) Analysis of an AC-DC Valley-fill Power Factor Corrector (VFPFC) 25 Fig.3: Frequency spectra of input currents of conventional rectifier and VFPFC at 200W output power The decrease in the harmonic distortion power and the fundamental reactive power for the fixed average power (Pavg ) gives higher power factor, and since there is rapid reduction in harmonic currents, THD is lowered as a result. Thirdly, the two small capacitors CIN1 and CIN2 serve to increase the conduction time of the input current by providing a path alternately for input current to flow into the VFPFC before the input line voltage rises above the VFPFC voltage and hence giving a decrease in current distortion. Fourthly, R2 and R3 are also used to suppress current distortion by limiting and smoothing the peak diode charging current. Though efficiency would drop a bit as power is being dissipated by those resistors, the average power loss by R2 and R3 is only a tiny fraction of input power. Experimental results in later session proved the prediction is correct. Fig. 4 displays the THD and power factor at different power levels for both rectifiers. The capacitors used in both cases are according to 10% output voltage drop during discharge period. 3. 2 THD and PF of different combinations of capacitors There are ten possible categories of VFPFC capacitors combinations as shown in Table 1. For different capacitors values the power factor and the THD% are also different. The set of combination with highest power factor and lowest THD is obtained when (C1=C4) (C2=C3). According to Fig. 5, the optimized capacitance values for highest power factor are obtained when C2=C3=1 /2 C1=1 /2 C4. 4. CIRCUIT DESIGN OF VFPFC 4. 1 Effective VFPFC capacitance The effective VFPFC capacitance Cef f is the combined capacitance of the VFPFC during the discharge period, which is equal to 3C/4. It is because Cef f = (C1//C3) + (C2//C4), for C1=C4=C and C2=C3=C/2. As discussed in Section 3.2, this set of capacitors obtains the highest PF and lowest THD. Fig.4: Comparison between conventional rectifier and VFPFC under same ripple voltage, (a) THD vs. output power and (b) Power factor vs. output power For a given output power Po , the estimated efficiency η, the normal discharge period tnormal and the holdup time requirement tholdup , the effective capacitance, Cef f , can be calculated from the following equation, Cef f = 2 · P0 · (tholdup + tnormal ) η(Vs2 − Vf2 ) (3) where Vs and Vf are the designated initial and final Cef f voltage, respectively, in the entire discharge period. The discharge period is the time from t4 to t6 of Fig. 2 (tnormal seconds) plus after the time t6 of Fig. 2 for tholdup seconds). 4. 2 Design curves of proposed VFPFC Fig. 6 gives some design curves for choosing different combinations of optimized valley-fill effective capacitance (Ceff) and resistance values (R2/R3) for highest power factor under different output power and power factor. These curves give only rough values although they are obtained from a number of simulation results. Accuracy of these curves will be justified by experimental results in Section 4.3. To design the VFPFC, the output power and the allowable output voltage drop during the discharge period should be determined first. The holdup start time should be chosen at a minimum value of VCef f during normal operation, i.e. after tnormal . After calculated Cef f from (3), then the input capacitors CIN0, CIN1 and CIN2 values are chosen from Fig 6(a). After that, the current limiting resistors R2 and R3 are selected from Fig. 6(b) according to desired power factor. The efficiency of the VFPFC due to these selected resistors are shown in Fig. 6(c). 26 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 Table 1: power Different combinations of VFPFC capacitances versus power factor and THD at 200W output 4. 3 Design example and experimental results The proposed VFPFC circuit, according to the observations in Sections 3.2, 4.1 and 4.3, is tested at the power level of 50W and input voltage of 110V(rms). tnormal is around 4ms for 50Hz AC input and tholdup is 5ms. Since the VFPFC starts discharge at around two-third of input voltage and assume 15% voltage ripple during discharge, we have Vs = 2 √ · 2 · 110 = 103.71 V (take100V ) 3 Vf = (1 − 0.15)Vs = 85V Cef f = 2 · 50 · (0.004 + 0.005) = 352µF 0.92(1002 − 852 ) 4 Cef f = 469µF (take470µF ) 3 Simulation and experimental results are given in Table 2. The input voltage, the input current and the output voltage of the experimental circuit are shown in Figs. 7(a) and 7(b). The measured power factor of the 50W VFPFC circuit is 0.95 and efficiency is 93%. From some simulation and experimental results shown above, there is very little difference between them. Although the design curves cannot definitely guarantee that “what you see what you get”, they are good enough as a rough design guide. Fig.5: Capacitance ratio, Ca/Cb (C2=C3=Ca & C1=C4= Cb) vs. Power factor, PF at 200W output power and 10% output voltage drop during discharge Table 2: Simulation data and measured data from experimental prototype C= 5. DISCUSSION Since the proposed PFC circuit has no inductor, which is the bulkiest and largest component for conventional PFC circuit like boost PFC converter, the size of the proposed circuit can be comparable to the existing ones. Beside, there is no switching loss associated with the circuit operation, the diode size can be further reduced comparing to the same rating of output power of active PFC circuits. Besides, normal standard diodes can be used as no switching is involved, hence the cost may also reduce. In addition, due to the advancement of semiconductor packaging, we may use dual-diode in a single package such as TO-220 for higher power application to minimize space. Since the main function of the PFC circuit is to im- Analysis of an AC-DC Valley-fill Power Factor Corrector (VFPFC) 27 with the VFPFC, the THD% is reduced dramatically, and the power factor is raised to an acceptable value. When compared with the LC filters for power factor correction, the VFPFC yields acceptable PF and THD% but with smaller size and weight. Design curves have been drawn to serve as a design tool for choosing appropriate capacitance and resistance values. References  (a)   (b)   (c) Fig.6: (a) Optimal values of VFPFC capacitances of CIN0, CIN1 and CIN2 for highest PF and lowest THD for output power range between 50W and 300W; (b) Current limiting resistance of R2/R3 for different power factor at different hold-up time requirement; (c) VFPFC efficiency according to resistances of R2/R3 selected from Fig. 6(b) prove the power factor, the output voltage contains substantial low frequency ripple which is the same as conventional boost PFC circuit and needs a postregulator to provide a smooth DC voltage as well as fast regulation. With the invention of recent wide input range DC/DC converters such as -, the proposed VFPFC will find more applications. 6. CONCLUSIONS A novel VFPFC has been proposed and analyzed. The operation of the circuit is depicted in detail. It is shown that by replacing the conventional rectifier     B. Sharifipour, J. S. Hung, P. Liao, L. Huber and M. M. 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(PESC) Proc., vol.4, pp. 2050-2055, 2002. K. Fujiwara and H. Nomura, “A power factor correction for single-phase diode rectifiers without employing PWM strategy,” International Power Electronics Conference (IPEC) Proc., vol. 3, pp. 1501-1506, 1995. I. Takahashi, T. Sato and M. Takeda, “Applications of nonlinear impedance circuit composed of diodes and capacitors or inductors”, IEE Industry Applications Society Annual Meeting, vol. 2, pp. 757-762, 1993. M.H. Todorovic, L. Palma, and P. Enjeti, “Design of a wide input range DC-DC converter with a robust power control scheme suitable for fuel cell power conversion”, IEEE Applied Power Electronics Conference and Exposition (APEC), Vol. 1, pp. 374 - 379, 2004. Xiangcheng Wang, Feng Tian, Yinxing Li, and I. Batarseh, “High Efficiency High Power Density DC/DC Converter with Wide Input Range”, IEEE Industry Applications Conference, 41st IAS Annual Meeting. Conference Record, Vol. 5, pp. 2115 - 2120, 8-12 Oct. 2006. 28 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 Fig.7a: Input voltage from AC mains (50V/div); Input current drawn by circuit (250mA/div) Fig.7a: Output voltage of the VFPFC (50V/div) Pisit Vanichchanunt received his B.Eng.(Hons) and Ph.D. degrees in Electronic and Information Engineering from The Hong Kong Polytechnic University, Hong Kong, in 1999 and 2004 respectively. In 2003, he joined PowereLab Limited, a spin-off company at The University of Hong Kong, as a Senior Engineer. His major responsibilities include project development and management, circuit design, and contribution of research in the area of power electronics. From 2006, he becomes a Lecturer in the School of Electrical and Information Engineering, The University of Sydney, Australia. He has published over 30 papers on the analysis and design of power electronics circuits. He holds one U.S. patent. His research interests include modeling, synthesis and computer-aided design of power converters, dc-dc converter for VRM application, electronic ballast, controls, power-factor-correction circuits, softswitching techniques and renewable electrical energy systems.