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5506 Fifth Avenue #D405 | Pittsburgh, PA 15232 | (412) 961 4435 | [email protected]
CARNEGIE MELLON UNIVERSITY – Dual Degree Master of Science in
Pittsburgh, PA
Electrical and Computer Engineering [GPA 3.56/4]
May 2016
Relevant Courses: Machine Learning, Analog IC Design, Energy Aware Computing, ULSI Technology, Computer Systems Programming
Engineering & Technology Innovation Management [ GPA 3.5/4]
Dec 2015
Bachelor of Engineering, Electrical and Electronics Engineering [GPA 8.55/10]
Bangalore, India
June 2011
SKILLSET – Circuit design, Design for Test, Layout & Schematic, Fabrication, C, Python, x86-architecture, Linux, Assembly Programming
EDA TOOLS & PLATFORMS - CADENCE VIRTUOSO, Spectre, PSpice, Multisim, MATLAB & Simulink, AUTOCAD, SniperSim, RAMmulator
Mixed-Signal Design for Test
Projects, Digital Systems Testing and Testable Design
Jan 2016 – Present
 Test generation and design for testability for digital circuits by identifying defect types like single stuck-line, fault simulation
 Implementing diagnosis and design projects for ATPG using D-Algorithm, PODEM and others in Python
Fabrication of AlN MEMS Resonator
Project, Micro and Nano Fabrications System
Jan 2016 – Present
 Synthesizing a MEMS device on a 4 inch Si wafer using fabrication steps like lithography, CMP, for integrated systems fabrication
System on Chip Technology(SC)
Project, Ultra Large Scale Integrated Technology (ULSI)
Aug 2015 – Present
 Designed a competitive SOC for 2020 on 7 nm FINFET, 3D integration and emerging PRAM memory technology
 Proposed a mobile platform SOC with ARM’s Big-Little (A72/A53) combination having comparable PPA to Exynos & A9
 Analysis on the new Global Foundries 22nm FDSOI for frequency – power tradeoffs, VDD choice, cache sizes and latency
Analog IC Design Projects
Design Projects, Analog Integrated Circuit Design
Aug – Dec 2015
 Designed, built and characterized 3- stage transimpedance amplifier with 50 MHz bandwidth, Opamp and a double-tail latch
comparator with a clock of 1.2 GHz and power consumption of 28 uW on 45 nm CMOS using Cadence Virtuoso
 Analysis including small signal, large signal and frequency domain with design trade-offs
 Schematic and layout design for CMOS using the GPDK process and layout design for 28 nm FINFET
Computer Systems Programming
Projects, Introductions to Systems Programming
Aug – Dec 2014
 Bit-level manipulations, IA32/64 calling conventions and stack organization, extensive gdb debugging based projects
 Built a cache simulator in C to understand memory hierarchy, impact of hits, misses and evictions based on LRU policy
INTERESTS - Hardware Design, Analog Circuit Design, SoC Design, Product Engineering, Product Management, Programming, Java
Freescale Semiconductor
Austin, Texas
Product & Technical Marketing Engineer Intern, Microcontrollers
May – August 2015
 Enhanced performance of wearable embedded device, the first of its kind from Freescale by examining characteristics of videos
 Performed board bring up activities and exploited ARM’s A9 and M0+ core to build an open source wearable platform
 Defined new features for latest version of the product which helped in incorporating the new NXP-NFC chip for small form-factor of
the board, technical documentation of the software manual for the wearable product
Larsen & Toubro Limited
Mumbai, India
Senior Engineer, Electrical & Automation Projects, International Division
June 2011 – July 2014
 Assessed, designed and assigned cost to reliable and safe switchgear products (primarily LV and MV Switchboards and allied
equipment) for various industry sectors like O&G, transport, process plants, etc.
 Managed weekly status reports for the GM when operating on multiple projects and coordinated with 5+ cross-functional
engineering teams to collect pertinent data to integrate and create a techno -commercial proposal
 Initiated and negotiated for technical and commercial aspects with clients resulting in the awarding of 10% of the projects
 Interacted directly with clients as well as front end engineers for technical and commercial solutions to improve product
 Delivered complete products to include thorough engineering documentation in 50% of the actual allotted time
Closed Order - Shah-Habshan-Ruwais Railway (Etihad Railways Phase 1) a/c Saipem, Abu Dhabi
Value about 1 Mn USD
Closed Order - Central Processing Facility a/c Gazprom, Badra Oil Field, Iraq (Iraqi Elite)
Value about 0.2 Mn USD
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