Mudit Bhargava

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Mudit Bhargava
Mudit Bhargava
5000 Forbes Avenue, Pittsburgh, PA 15213
 [email protected] |  412-519-2046
Webpage: http://www.andrew.cmu.edu/~mbhargav
PhD candidate, Department of ECE, Carnegie Mellon University (CMU). Advisor: Prof. Ken Mai.
Expected date of graduation: May, 2013.
Research interests: VLSI design, memory design, high performance digital circuits, hardware security.
4+ yrs. of industrial exp. Worked on 5 tapeouts at CMU. Conference publications: 9. Patents: 2 granted, 2 filed.
 Freescale Semiconductors, Austin (Summer internship, 2008)
 Evaluation of post-silicon offset compensation techniques in sense amplifiers in 32nm SRAMs.
 Wafer probed our 45nm bulk CMOS testchip.
 ST Microelectronics, Greater Noida, India (2002-2006)
 Design Engineer in Embedded SRAM Design Group. Worked on various projects on the design of SRAM compilers, both single-port and dualport, targeted for power, area, and/or performance in 130nm, 90nm, & 65nm. Part of four successful SRAM compiler design projects.
 Granted two patents related to work in SRAMs (US20070201287 and US20080143390).
 Led two in-house research projects (i) Novel sense amplifier designs (ii) Circuit & layout level solutions for electromigration mitigation.
 Carnegie Mellon University (CMU), Pittsburgh (2006 - present)
 PhD candidate advised by Prof Ken Mai (Department of Electrical and Computer Engineering)
 Expected date of graduation: May 2013.
 GPA 3.91/4.00.
 PhD Thesis Research: “Reliable, Secure, Efficient Physical Unclonable Functions.” A Physical Unclonable Function (PUF) is a security
primitive that is increasingly becoming popular for applications like identification, authentication, and secret key generation. Leveraging the
randomness in the underlying process variations, a PUF, when provided with a challenge, generates a response that is die-specific (unique),
consistent across multiple evaluations (reliable), and that cannot be modeled (random). The goal of the research is to design an efficient,
secure and reliable PUF system. To that end, we designed two testchips in 65nm bulk CMOS. The 1 generation testchip (fabricated in Nov
2010) had custom designed PUF core structures to perform an apples-to-apples comparison of security and VLSI metrics of several PUF
types (including a novel sense amplifier based PUF). The 2 generation testchip (fabricated in Jun 2012) had many improved test-structures
and novel designs, including a PUF system prototype and other structures to evaluate baseline reliability enhancement techniques.
 Other Research Projects:
- Robust SRAM design (65nm testchip): Implementation of multi-bit ECC schemes using erasure coding and 2D coding. A custom high
performance hierarchical 128kb SRAM was designed, capable of read before write, configurable & separate self-timing for read & write, inbuilt address decoding check using an integrated ROM array, and a valid bit with 1-cycle entire memory invalidation. Currently being tested.
- Secure Chip Odometers (65nm simulations): Circuits that gauge the age of a chip using phenomena like electromigration, NBTI, and HCI.
- Secure AES S-box (65nm simulations): Differential Power Analysis (DPA) resistant ROM-based S-box implementation in AES.
- SRAM Virtual Prototyping tool (CAD project): Based on user provided specifications (e.g., area, power, performance), the tool generates a
virtual prototype of an SRAM using canonical and user-provided building blocks, chosen based on underlying analytical models.
- In-situ SRAM characterizer (45nm testchip): Circuits to measure IREAD, IOFF, ILEAK, read/write margins of 6T SRAM & sense amplifier offset.
- Offset compensation in SRAM sense amplifiers (45nm testchip): Low-overhead, coarse correction of offset using offset `kicks’.
- Sub-threshold SRAM designs (90nm simulations/layout): Comparison of existing and some novel designs to achieve the optimal cell design.
 Indian Institute of Technology (IIT), Kharagpur, India (1998-2002)
 Bachelors of Technology in Department of Electronics and Electrical Communications Engineering (E&ECE)
 GPA 8.4/10.0
US20070201287: “Programmable delay introducing circuit in self-timed memory”, N.Kohli, M.Bhargava, S.Kumar.
US20080143390: “Sense amplifier providing low capacitance with reduced resolution time”, A.Goel, M.Bhargava, S.Kumar.
Disclosure filed: “On-chip hardware structures to securely measure integrated circuit age and usage”, M.Bhargava, K.Mai.
Disclosure filed: “Techniques for improving the reliability of physical unclonable functions via integrated circuit aging
phenomena”, M.Bhargava, K.Mai.
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 M.Bhargava, C.Cakir, K.Mai, “Comparison of Bi-stable and Delay-based Physical Unclonable Functions from Measurements in
65nm bulk CMOS”, IEEE Custom Integrated Circuits Conference (CICC) 2012. Awarded Intel/Analog Devices/Catalyst Foundation
CICC Student Scholarship award for submitting ‘one of the highest rated student papers’. [pdf]
C. Cakir, M.Bhargava, K.Mai, “6T SRAM and 3T DRAM Data Retention and Remanence Characterization in 65nm bulk CMOS”,
IEEE Custom Integrated Circuits Conference (CICC) 2012. Awarded CICC Student Scholarship award for submitting ‘one of the
highest rated student posters’. [pdf]
M.Bhargava, C.Cakir, K.Mai, “Reliability Enhancement of Bi-Stable PUFs in 65nm Bulk CMOS,” IEEE Hardware-Oriented Security
and Trust (HOST) 2012. [pdf]
M.Bhargava, C Cakir, K.Mai, “Circuit Implementations of Physical Unclonable Functions,” SRC TECHCON 2011.
M.Bhargava, C.Cakir, K.Mai, “Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability
of PUF responses”, IEEE Hardware-Oriented Security and Trust (HOST) 2010. [pdf]
C.Teegarden, M.Bhargava, K.Mai, “Side-channel attack resistant ROM-based AES S-Box,” IEEE Hardware-Oriented Security and
Trust (HOST) 2010. [pdf]
M.Bhargava, C.Cakir, K.Mai, “Sense amplifier based PUFs,” SRC TECHCON 2010.
S.Nalam, M.Bhargava, K.Mai, B.H.Calhoun, “Virtual Prototyper (ViPro): an early design space exploration and optimization tool
for SRAM designers,” Design Automation Conference (DAC) 2010. [pdf]
M.Bhargava, M.P.McCartney, A.Hoefler, K.Mai, “Low-overhead, digital offset compensated, SRAM sense amplifiers,” IEEE
Custom Integrated Circuits Conference (CICC) 2009. Awarded AMD/CICC Student Scholarship award for submitting ‘one of the
highest rated student papers’. [pdf]
M.Bhargava, S.V.Nalam, B.Calhoun, K.Mai, “An SRAM prototyping tool for rapid sub-32nm design exploration and
optimization,” SRC TECHCON 2009.
U.Arslan, M.P.McCartney, M.Bhargava, X.Li, K.Mai, L.Pileggi, “Variation-tolerant SRAM sense-amplifier timing using configurable
replica bitlines,” IEEE Custom Integrated Circuits Conference (CICC) 2008. [pdf]
S.V.Nalam, M.Bhargava, Ken Mai, B.H.Calhoun, “A technology-agnostic simulation environment (TASE) for iterative custom IC
design across processes,” IEEE International Conference on Computer Design (ICCD) 2009. [pdf]
M.Bhargava, K.Mai, “SRAM circuit characterizer,” Presentation, Student Work-in progress, IEEE International Solid-State Circuits
Conference (ISSCC) 2008.
18722 (K.Mai)
18730 (V.Gligor)
18741 (B.Falsafi)
18623 (L.Pileggi)
18765 (S.Blanton)
36625 (A.Lee)
18869 (X.Li)
18760 (R.Rutenbar)
18769 (A.Strojwas)
Advanced Digital Circuit Design
Introduction to Computer Security
Advanced Computer Architecture
Analog Circuit Design
Digital Systems Testing and Testable Design
Probability and Mathematical Statistics
Statistical IC Design
VLSI CAD: Logic to Layout
Design for Manufacturability in Nanometer Era
 Programming: C, C++, Perl, MATLAB.
 CAD Tools: Cadence Virtuoso platform, Allegro, KiCad, ModelSim, Mentor Graphics Calibre, NI-VISA.
 Simulators: Spectre, UltraSim, Eldo, HSIM, Nanosim, SPICE.
 Cricket: Captain of CMU team (2012). Captain of Kent Cricket Club, Pittsburgh Cricket Association (PCA) in 2012. Won PCA
championship in 2010, 2011 (15+ teams). Awarded ‘MVP, Playoffs’ in 2011 PCA Tournaments.
 Indian Graduate Students Association (IGSA), Carnegie Mellon University: Membership Chair (2007-08), V. President (2008-09).
 Dramatics: Captain of IGSA Dramatics Club: 2007-2010. Co-directed, co-wrote, and acted in four plays.
References available on request
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